Acta Scientific Computer Sciences

Literature Review Volume 4 Issue 6

Design and Synthesis of Windowed Watchdog Timer for High Speed Memory Applications

Neeraj Kumar Misra* and T Swetha

Department of Electronics and Communication Engineering, Bharat Institute of Engineering and Technology, Hyderabad, India

*Corresponding Author: Neeraj Kumar Misra, Department of Electronics and Communication Engineering, Bharat Institute of Engineering and Technology, Hyderabad, India.

Received: April 04, 2022; Published: May 25, 2022


Because embedded systems are utilised in such a broad variety of security-related applications, it is imperative that they have an exceptionally high level of dependability in order for them to operate correctly. External watchdog timers are used in these systems so that time-related problems may be automatically handled and recovered from in the event that they arise. The bulk of the external watchdog clocks now available on the market have a limited number of activities that they can do since adjusting their timeout durations requires extra circuitry in most cases. A watchdog timer that has been developed and is suitable for use in memory-related applications such as data storage is discussed in this work. A Verilog HDL-based design was used to develop the system, and a Verilog-based simulation was used to create it using Xilinx ISE 14.7. Both of these were written in Verilog.

Keywords: Low Power VLSI; Windowed Watch Dog Timer; Memory


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Citation: Neeraj Kumar Misra and T Swetha. “Design and Synthesis of Windowed Watchdog Timer for High Speed Memory Applications". Acta Scientific Computer Sciences 4.6 (2022): 54-58.


Copyright: © 2022 Neeraj Kumar Misra and T Swetha. This is an open-access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.


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